| The |
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The truth table of each individual gate is:
| input B | input A | output |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
| NOR gate truth table |
where '0' represents a LOW voltage, and '1' represents a HIGH voltage.
You can investigate the behaviour of a single NOR gate using this circuit:
| NOR gate test circuit |
The inputs of the gate must be connected, either to LOW or to HIGH, and must not be left open circuit. This is the function of the input switches with their pull-down resistors. To avoid loading the output of the gate, a transistor switch indicator circuit should be used.
It is good practice with CMOS circuits to insert a decoupling capacitor, 47 µF or 100 µF, across the power supply. (This helps to prevent the transfer of spikes along the power supply rails.)
Here is the circuit on prototype board:
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In the prototype circuit, it is not essential to make connections to the unused gates. However, in any final circuit, all unused CMOS inputs must be connected either to HIGH or to LOW. Make it an absolute rule that CMOS inputs are never left open circuit.
There is no problem with CMOS outputs. Worry about the inputs and leave any unused outputs unconnected.
An important property of NOR gates is that they can be linked to perform the functions of other logic gates. In fact, any logic function can be implemented using only NOR gates:
| NOR gate circuits for other logic gates |
If you have designed a system which contains a NOR gate integrated circuit, it can be convenient and cost-effective to implement other logic functions using spare NOR gates which would otherwise be unused.
As an example, here is the prototype board layout for an AND gate built with NOR gates:
Work through the truth table combinations to confirm that this circuit obeys the truth table for AND. Modify the circuit to make a NAND gate.
What happens when NOR gates are linked like this?
| Cascading NOR gates |
Work out the truth table for this circuit. When you do this, you will discover that the circuit does not give the truth table for a 3-input NOR gate. Unlike AND and OR gates, NOR gates cannot be cascaded in this way.
It is possible to make a 3-input NOR gate using 2-input NOR gates, but the circuit requires an extra gate:
| 3-input NOR gate |
The truth table for this circuit is:
| input C | input B | input A | output |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 0 |
3-input, 4-input, and 8-input NOR gates are available in integrated circuit form, as listed in the links section.
A useful application of NOR gates is to make a SET/RESET bistable, latch, or flip-flop. Here is the circuit:
| NOR gate bistable |
Once again, notice that you must have a switch/resistor voltage divider at the inputs to the NOR gates. With a NOR gate latch, the inputs are held LOW and pulsed HIGH. This means that you need pull-down resistors. Compare this circuit with a SET/RESET latch bistable built using NAND gates.
To avoid loading the outputs of the latch, transistor switch/LED indicators are used. It is a common mistake to connect LEDs directly to the latch outputs:
| Bad circuit: directly connected LEDs take too much current from the outputs of the latch |
Even with current-limiting resistors connected in series with the LEDs, this circuit might not work because the LEDs take too much current from the ouptuts of the latch so that the output voltages are pulled downwards and may not count as HIGH when they are supposed to be HIGH.
If you connect LEDs without current-limiting resistors, the circuit cannot possibly work.
Here is the correct circuit on prototype board:
When the power supply is first connected, you can't predict whether the latch will be SET or RESET.
Operate the switches one at a time to see the circuit in action. When the latch is SET, what happens if you press the SET button again?
If you press both switches, both LEDs will be OFF. This follows from the truth table for an individual NOR gate. You won't be able to release both switches simultaneously, so that the latch will flip one way or the other when you let go.
The behaviour of the circuit can be summarised in truth table form:
| SET | RESET | Q | NOT-Q |
| 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 0 | 0 | 1 |
| 1 | 1 | 0 | 0 |
| 0 | 0 | ? | ? |
This is a different sort of truth table in which the sequence of events is recorded. In the first line, neither switch is pressed and the bistable is in its RESET state.
In the second and third lines the SET switch is pressed and then released. The bistable is forced into its SET state and remains SET when the switch is released.
Operating the RESET switch puts the bistable into its RESET state, fourth line. When the RESET switch is released, the bistable remains in its RESET state, fifth line.
The last two lines show what happens if both switches are pressed. This is known as a disallowed state because the next stage in the sequence cannot be predicted.
The NOR gates aren't damaged by pressing both switches at the same time. However, since nothing useful happens, circuits which use SET/RESET bistables are designed to avoid the disallowed state.
The links below allow you to download documents in
Adobe Acrobat ©, PDF, format. In the unlikely event that you don't already have Acrobat Reader, you can download the latest version direct from Adobe:
4001B data sheet (NXP, 2008)
4001B data sheet (ST Microelectronics, 2004)
4002 4-input NOR
4025 3-input NOR
4078 8-input NOR