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4011B Quad 2-input NAND gates hot stuff !! hot stuff !! hot stuff !!



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1. Pin connections

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4011B pin connections

The 4011 available from Rapid Online has four separate 2-input NAND gates which you can use independently.

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2. Truth table

The truth table of each individual gate is:

input B input A output
0 0 1
0 1 1
1 0 1
1 1 0
NAND gate truth table

where '0' represents a LOW voltage, and '1' represents a HIGH voltage.

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3. Basic operation.


You can investigate the behaviour of a single NAND gate using this circuit:

NAND gate test circuit

The inputs of the gate must be connected, either to LOW or to HIGH, and must not be left open circuit. This is the function of the input switches with their pull-down resistors. To avoid loading the output of the gate, a transistor switch indicator circuit should be used.

It is good practice with CMOS circuits to insert a decoupling capacitor, 47 µF or 100 µF, across the power supply. (This helps to prevent the transfer of spikes along the power supply rails.)

  •   Beasties need power supplies! Don't forget to connect pin 14 of the 4011 to +9 V and pin 7 to 0 V.

Here is the circuit on prototype board:


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down open in a new window 4011 pins 4011B NAND gate test circuit

In the prototype circuit, it is not essential to make connections to the unused gates. However, in any final circuit, all unused CMOS inputs must be connected either to HIGH or to LOW. Make it an absolute rule that CMOS inputs are never left open circuit.

There is no problem with CMOS outputs. Worry about the inputs and leave any unused outputs unconnected.

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4. Other gates made with NAND

An important property of NAND gates is that they can be linked to perform the functions of other logic gates. In fact, any logic function can be implemented using only NAND gates:

NAND gate circuits for other logic gates

If you have designed a system which contains a NAND gate integrated circuit, it can be convenient and cost-effective to implement other logic functions using spare NAND gates which would otherwise be unused.

As an example, here is the prototype board layout for an OR gate built with NAND gates:

down up open in a new window 4011 pins OR gate built using NAND gates

Work through the truth table combinations to confirm that this circuit obeys the truth table for OR. Modify the circuit to make a NOR gate.

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5. Cascading

What happens when NAND gates are linked like this?

Cascading NAND gates

Work out the truth table for this circuit. When you do this, you will discover that the circuit does not give the truth table for a 3-input NAND gate. Unlike AND and OR gates, NAND gates cannot be cascaded in this way.

It is possible to make a 3-input NAND gate using 2-input NAND gates, but the circuit requires an extra gate:

3-input NAND gate

The truth table for this circuit is:

input C input B input A output
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

3-input, 4-input, and 8-input NAND gates are available in integrated circuit form, as listed in the links section.

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6. NAND gate bistable

A useful application of NAND gates is to make a SET/RESET bistable, latch, or flip-flop. Here is the circuit:

NAND gate bistable

Once again, notice that you must have a switch/resistor voltage divider at the inputs to the NAND gates. With a NAND gate latch, the inputs are held HIGH and pulsed LOW. This means that you need pull-up resistors. Compare this circuit with a SET/RESET latch bistable built using NOR gates.

To avoid loading the outputs of the latch, transistor switch/LED indicators are used. It is a common mistake to connect LEDs directly to the latch outputs:

Bad circuit: directly connected LEDs take too much current from the outputs of the latch

Even with current-limiting resistors connected in series with the LEDs, this circuit might not work because the LEDs take too much current from the ouptuts of the latch so that the output voltages are pulled downwards and may not count as HIGH when they are supposed to be HIGH.

If you connect LEDs without current-limiting resistors, the circuit cannot possibly work.

Here is the correct circuit on prototype board:

up open in a new window 4011 pins NAND gate bistable

When the power supply is first connected, you can't predict whether the latch will be SET or RESET.

Operate the switches one at a time to see the circuit in action. When the latch is SET, what happens if you press the SET button again?

If you press both switches, both LEDs will be ON. This follows from the truth table for an individual NAND gate. You won't be able to release both switches simultaneously, so that the latch will flip one way or the other when you let go.

The behaviour of the circuit can be summarised in truth table form:

1 1 0 1
0 1 1 0
1 1 1 0
1 0 0 1
1 1 0 1
0 0 1 1
1 1 ? ?

This is a different sort of truth table in which the sequence of events is recorded. In the first line, neither switch is pressed and the bistable is in its RESET state.

In the second and third lines the SET switch is pressed and then released. The bistable is forced into its SET state and remains SET when the switch is released.

Operating the RESET switch puts the bistable into its RESET state, fourth line. When the RESET switch is released, the bistable remains in its RESET state, fifth line.

The last two lines show what happens if both switches are pressed. This is known as a disallowed state because the next stage in the sequence cannot be predicted.

The NAND gates aren't damaged by pressing both switches at the same time. However, since nothing useful happens, circuits which use SET/RESET bistables are designed to avoid the disallowed state.

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7. Links

reference book..

7.1 Data sheets

The links below allow you to download documents in Adobe Acrobat ©, PDF, format. In the unlikely event that you don't already have Acrobat Reader, you can download the latest version direct from Adobe:

open document 4011B data sheet (NXP, 1995)

open document 4011B data sheet (ST Microelectronics, 2004)

7.2 DOCTRONICS links

4012 4012 4-input NAND

4023 3-input NAND

4068 8-input NAND

4093 4093 Schmitt 2-input NANDnew

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