Dual D-type flip-flops
|Technology: CMOS||Power supply: 3-15 V||
|Pin connections||2-bit counters|
|About D-type flip-flops||Application idea|
|Basic operation||LINKS . . .|
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The 4013 has two D-type flip-flops, which
A D-type flip-flop, also called a D-type bistable, is a subsystem with two stable states. Using appropriate input signals, you can trigger the flip-flop from one state to the other.
The diagram below shows the input and output connections of a single D-type bistable:
and are the outputs of the bistable. The logic states of the outputs are always opposite.
|The bistable is SET when and , and RESET when and .|
The D-type has four inputs. These are:
DATA input: This is connected either to a LOW voltage, logic 0, or to a HIGH voltage, logic 1.
CLOCK input: The triangle, , next to the CLOCK input shows that it is edge-triggered, that is, it responds to sudden changes in voltage, but not to slow changes or to steady logic levels. The CLOCK input of the 4013 D-type bistable is rising-edge triggered, meaning that it responds only to a sudden change from LOW to HIGH.
Usually, the CLOCK input is connected to a subsystem which delivers pulses. To test the 4013, you will need to build an astable.
SET input: The SET input is normally held LOW. When it is pulsed HIGH, the outputs of the bistable are forced immediately to the SET state, , .
RESET input: The RESET input is normally held LOW. When it is pulsed HIGH, the outputs of the bistable are forced immediately to the RESET state, ,
To explain the behaviour of the D-type bistable, you can learn to say that:
|The logic state at the DATA input is transferred to the output on the rising edge of the CLOCK signal.|
This is a precise description of the function of the D-type.
You can understand what a D-type bistable does by building a circuit in which the output is connected back to the D - input:
This arrangement is called a toggle flip-flop, or toggle bistable.
Here is the circuit diagram for a practical circuit:
The inputs of the D-type must be connected, either to LOW or to HIGH, and must not be left open circuit. This includes the SET and RESET inputs which are connected to 0 V. To avoid loading the output of the D-type, a transistor switch indicator circuit is used. It is good practice with CMOS circuits to insert a decoupling capacitor, 47 µF or 100 µF, across the power supply. (This helps to prevent the transfer of spikes along the power supply rails.)
Don't forget - - Connect pin 14 of the 4013 to +9 V and pin 7 to 0 V.
Build the circuit on prototype board following the diagram below:
When you connect the power supply, the LEDs will flash slowly enough for you to interpret what is going on. With and D linked, the D-type bistable changes state every time a clock pulse is received. This can be illustrated using voltage/time, V/t graphs:
To start with, both the CLOCK signal and the output of the D-type are LOW, logic 0. Since the and outputs are opposite, must be HIGH, logic 1. Because the DATA input, D, is connected to , it is also HIGH.
When the first rising edge arrives, the logic state at D is transferred to the output, which goes HIGH in turn. This transfer involves a very short time delay, just a few nanoseconds. When goes HIGH, goes LOW, and D goes LOW.
When the second rising edge arrives, D is LOW and so the output becomes LOW, making D HIGH again, ready for the next rising edge and so on.
As you can see, the number of pulses at the output of the bistable is divided by two compared with the number of pulses at the input. A toggle bistable is a divide-by-two counter, or 1-bit binary counter.
What happens if you add a second toggle bistable after the second? The circuit becomes:
This is a lot simpler to set up than it looks! All you need to do is to add a few extra components and links to your existing prototype circuit:
Up to previous stage
Check the sequence of the LEDs:
The second D-type divides by two again, giving pulses at one quarter of the frequency of the CLOCK signal. The outputs of the D-types follow the sequence:
|output Q2||output Q1|
Can you see that the outputs give the binary numbers from 1 1 to 0 0 in descending order? The circuit you have constructed is a 2-bit binary DOWN counter.
You can modify the circuit to make a 2-bit binary UP counter. To do this, insert a NOT gate, using one of the spare gates from the 4093, and link from the output of the first D-type to the CLOCK input of the second (replacing the link from to CLOCK):
The prototype board layout becomes:
Up to previous stage
Check that the LEDs follow the V/t graph pattern for a 2-bit binary up counter:
From these graphs it looks as if the D-types might be triggered by the falling edges of the previous stage. To make an UP counter, the output of each bistable is connected to the CLOCK input of the next stage. The outputs are doing exactly the opposite of the outputs, so the D-types are rising edge triggered, as before.
D-type bistables can easily be used to make a combination lock. Using two 4013 integrated circuits, you can make a 4-digit combination lock in which the keys representing the code digits must be entered in the correct order. Pressing the key for any digit which is not part of the code RESETs all four D-types:
The D-input of the first D-type is held HIGH. When the first digit of the combination is pressed, output goes HIGH. If the second digit is the next key presssed, the second D-type will be SET and so on. Pressing any of the unselected keys gives a HIGH at the RESET inputs of all four bistables, and all the outputs revert to LOW.
Once the four digits of the code have been entered in the correct sequence, the lock ouptut goes HIGH and will remain HIGH until an unselected key is pressed. The system could be extended to provide an automatic RESET after a delay. Which type of subsystem could you use?
Cross references in the Beastie Zone:
4001 NOR bistable, 4011 NAND bistable
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