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4014

8-stage shift register

bst_16.gif (2262 bytes)


Technology: CMOS

Power supply: 3-15 V

16-pin DIL


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Navigation

Pin connections Basic operation
What is a shift register? Applications
Parallel loading
Shift register variants LINKS . . .

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Pin connections

4014 pin connections

The 4014 is a fully synchronous 8-bit shift
register with eight parallel inputs
(P0-P7),
a serial data input
(DS), a LOW to HIGH
edge-triggered clock input
(CP) and parallel
outputs from the last three stages
(O5-O7).

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What is a shift register?

A shift register consists of a chain of bistables connected together so that data can be transferred (shifted) along the chain from one end to the other. The diagram shows a 4-bit shift register made from D-type bistables:

circuit for a 4-bit shift register

click for simulation Click the button for a Crocodile Technology simulation of this circuit.

Can you see that the CLOCK inputs of all the D-types are connected together? This is a key feature of the circuit of a shift register. Suppose all the D-types have been reset, that is A=0, B=0, C=0 and D=0. Now suppose that the SERIAL INPUT (DS) is made HIGH.

What will happen when pulses are applied to the CLOCK input? On the first rising edge, also called a LOW to HIGH transition, the logic state at the SERIAL INPUT is transferred to A, the output of the first D-type. This happens after a short delay, known as the propagation delay of the D-type. Before this change, the logic state at the D-input of the second D-type was LOW, logic 0. This 0 is transferred to B. In other words, no change in logic state is observed.

When the next CLOCK pulse arrives, The SERIAL INPUT and the D-input of the second D-type are both at logic 1. Output A remains at 1 and output B becomes 1. Each new pulse tranfsers the logic 1 signal to the next stage of the shift register. You can follow these changes in logic levels from the V/t graphs given in the next diagram:

shift register V/t graphs

An interesting variation of the shift register circuit is the ring counter, or Johnson counter, shown below:

ring counter (Johnson counter)

click for simulation Click the button for a Crocodile Technology simulation of this circuit.

The connection from NOT-Q back to the SERIAL INPUT of the shift register prevents the shift register from getting stuck in any particular state. The outputs follow a definite sequence. With four D-types, there are 2x4=8 different output states:

ring counter V/t graphs

Ring counters show the action of shift registers clearly. The sequence produced has 2n different states, where n is the number of D-types. The 4017 decade counter contains a 5-stage ring counter with its outputs decoded to provide 10 individual outputs.

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Parallel loading

The simplest shift registers have a single SERIAL INPUT where all the data must be loaded in. To make the output of the third D-type go HIGH, you need to load a 1 at the SERIAL INPUT and then deliver three clock pulses to move the 1 along to where you want it to be. Parallel loading allows you to load a 1 directly to the output of the third D-type and simultaneously to set the values of all the other bits stored by the shift register.

The 4014 provides synchronous parallel loading. This means that the parallel data is loaded on the rising edge of the next clock pulse, in just the same way as for serial transfer between stages:

synchronous parallel loading

click for simulation Click the button for a Crocodile Technology simulation of this circuit.

Gating is not required at the first input because the SERIAL INPUT is equivalent to P0 when parallel loading is synchronous.

When PARALLEL LOAD ENABLE is LOW, the output of the NOT gate is HIGH. This enables the first AND gate, so that the logic state which appears at output A is transferred, via the OR gate to the D-input of the second bistable. Note that the output of the second AND gate is held LOW. In a similar way, output B is transferred to the D-input of the next bistable, allowing the shift register to operate normally.

When PARALLEL LOAD ENABLE is HIGH, the output of the NOT gate is LOW and serial transfer is not enabled. Instead, the second AND gate of each pair is enabled and the PARALLEL LOAD INPUTS are transferred to the D-inputs of the bistables. This operation is synchronous. The outputs of the shift register do not chnage until there is a rising edge at the CLOCK INPUT.

You might like to confirm for yourself that the three NAND gates shown for the last stage of this shift register perform exactly the same logic function as two AND gates followed by OR.

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Shift register variants

Now that you know a bit more about shift registers, you will have no difficulty in understanding the differences between four shift register variants known as SISO (serial in/serial out), SIPO (serial in/parallel out), PISO (parallel in/serial out) and PIPO (parallel in/parallel out). The electronic circuits inside these devices are likely to be very similar, but the external connections available to the user are not the same:

shift register variants

PIPO registers are the most versatile because all the connections you are likely to want are available externally. The 4014 is essentially a PISO register, although outputs O5 and O6 are available in addition to the SERIAL OUTPUT, O7.

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Basic operation

To investigate the 4014, you need to provide binary inputs which are easily changed. In the prototype circuit shown below the P0-P7 parallel input values are set by an 8-way DIL switch. DIL stands for dual-in-line. The pins of the switch are arranged in two rows on a 0.1 in matrix and fit across the gap at the right hand side of the prototype board. The switches are operated with the aid of a small screwdriver. Moving the slider to the right, into the ON position, closes the switch and connects the corresponding input to a HIGH voltage. In the OFF position, the switch is open and the input becomes LOW. This is the effect of the 10 kW pull down resistors.

click for pins! 4014
4014 shift register test circuit

To test the circuit, press the SERIAL INPUT switch. You need to keep the switch pressed until the next rising edge at the CLOCK input, indicated by the flashing LED at the top of the prototype board. The lower LED should illuminate after a delay equivalent to seven additional clock pulses. The next clock pulse turns the output LED OFF.

To investigate parallel loading, set the desired input pattern on the DIL switches and press the parallel load enable switch. Again, you need to keep the switch pressed until the next rising edge. The SERIAL OUTPUT LED will now flash following the input pattern as the data is transferred along the shift register.

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Applications

The most obvious application for a PISO, parallel in/serial out, shift register like the 4014 is as a parallel to serial converter. These are used in communication systems where information is to be transferred one bit at a time along a single communication link, such as a fibre optic cable.

For designing simple projects, shift registers with parallel outputs are more useful. You can find out about some of these applications by following the links in the next section.

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LINKS

Cross references in the Beastie Zone:

4013 Dual D-type flip-flop
4015
Dual 4-stage shift register
4021 8-bit static shift register


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