Dual 4-stage shift register

bst_16.gif (2262 bytes)

Technology: CMOS

Power supply: 3-15 V

16-pin DIL


Pin connections Basic operation
What is a shift register? Applications
Shift register variants LINKS . . .

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Pin connections

4015_01.wmf (25906 bytes)

The 4015 contains two 4-bit shift registers
which can be used independently, or
linked to provide an 8-bit register.
Each register has a serial data input
a clock input (CP), four parallel outputs
(O0-O3) and a reset input (MR).

Register B connections bold.


What is a shift register?

A shift register consists of a chain of bistables connected together so that data can be transferred (shifted) along the chain from one end to the other. The diagram shows a 4-bit shift register made from D-type bistables:

circuit for a 4-bit shift register

click for simulation Click the button for a Crocodile Technology simulation of this circuit.

Can you see that the CLOCK inputs of all the D-types are connected together? This is a key feature of the circuit of a shift register. Suppose all the D-types have been reset, that is A=0, B=0, C=0 and D=0. Now suppose that the SERIAL INPUT (DS) is made HIGH.

What will happen when pulses are applied to the CLOCK input? On the first rising edge, also called a LOW to HIGH transition, the logic state at the SERIAL INPUT is transferred to A, the output of the first D-type. This happens after a short delay, known as the propagation delay of the D-type. Before this change, the logic state at the D-input of the second D-type was LOW, logic 0. This 0 is transferred to B. In other words, no change in logic state is observed.

When the next CLOCK pulse arrives, The SERIAL INPUT and the D-input of the second D-type are both at logic 1. Output A remains at 1 and output B becomes 1. Each new pulse tranfsers the logic 1 signal to the next stage of the shift register. You can follow these changes in logic levels from the V/t graphs given in the next diagram:

shift register V/t graphs

An interesting variation of the shift register circuit is the ring counter, or Johnson counter, shown below:

ring counter (Johnson counter)

click for simulation Click the button for a Crocodile Technology simulation of this circuit.

The connection from NOT-Q back to the SERIAL INPUT of the shift register prevents the shift register from getting stuck in any particular state. The outputs follow a definite sequence. With four D-types, there are 2x4=8 different output states:

ring counter V/t graphs

Ring counters show the action of shift registers clearly. The sequence produced has 2n different states, where n is the number of D-types. The 4017 decade counter contains a 5-stage ring counter with its outputs decoded to provide 10 individual outputs.


Shift register variants

Now that you know a bit more about shift registers, you will have no difficulty in understanding the differences between four shift register variants known as SISO (serial in/serial out), SIPO (serial in/parallel out), PISO (parallel in/serial out) and PIPO (parallel in/parallel out). The electronic circuits inside these devices are likely to be very similar, but the external connections available to the user are not the same:

shift register variants

PIPO registers are the most versatile because all the connections you are likely to want are available externally. Each of the two 4015 registers is a SIPO register, with all of the outputs available externally.


Basic operation

In the prototype circuit shown below, clock pulses are provided by a Schmitt trigger NAND gate astable. The clock pulses are connected to the clock inputs of both 4-bit registers, CPA and CPB. The serial data input, DA of the first register is connected to a push button switch input, allowing you to decide whether the serial input will be LOW (switch not pressed), or HIGH (switch pressed).

The final output of the first register, O3A is connected to the serial input, DB, of the second register, to form an 8-bit shift register. All the outputs are connected to transistor/LED indicators on the lower prototype board:

click for pins! 4015
4015 test circuit: click for next stage

Be careful to identify the outputs of the shift registers correctly. Each side of the integrated circuit has three outputs from one of the registers and one output from the other!

To investigate the action of the shift register, press the SERIAL INPUT switch and wait for the next rising edge, indicated by the flashing LED. The register output LEDs show the pattern of transfer from stage to stage within the shift register.

It is easy to rearrange the circuit to make a ring counter:

click for pins! 4015
4015 8-stage ring counter: click for next stage

click to return Up to previous stage

How many different states does this ring counter generate?



An interesting shift register variation is the pseudo-random sequence generator. Exclsuive-OR gates are connected to the outputs of some of the stages, as follows:

8-stage pseudo-random sequence generator

A pseudo-random sequence eventually repeats. However, a short sample of the 0's and 1's at the SERIAL OUTPUT will appear to be random. The length of the sequence depends upon the points selected as inputs for the exclusive OR gates. The maximum sequence length is 2n-1, where n is the number of D-types.

If the outputs are all 0's, the shift register becomes locked into its reset state. This is prevented by the 1 MW and the 10 mF capacitor. If the SERIAL OUTPUT remains at logic 0 for too long, the capacitor slowly charges up. When the D input of the first flip-flop becomes a 1, the pseudo-random sequence will restart.

You can investigate the pseudo-random sequence generator by modifiying the previous circuit. Remove the switch and the 10 kW used to provide the SERIAL INPUT and replace these with a 1 MW pull up resistor, with links as shown:

click for pins! 4015
4015 pseudo-random sequence generator

click to return Up to previous stage

Make connections to the 4040 exclusive OR gates from O3A, O0B, O1B and O3B and complete the circuit by adding the 1 mF capacitor and a transistor/LED indicator, together with all the remaining links.

This circuit generates a pseudo-random sequence of 0's and 1's at the SERIAL OUTPUT. You can speed the sequence up by changing the frequency of the clock pulses from the 4093 astable. Try replacing the 1 mF capacitor next to the 4093 with a smaller value. The sequence starts to repeat after 255 clock pulses.



Cross references in the Beastie Zone:

4013 Dual D-type flip-flop
8-stage shift register
4021 8-bit static shift register

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