Doctronics

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Discovering Digital Electronics


 3 : ASTABLES

Astable circuits produce pulses. In this Chapter, you can find out how astables work and experiment with some of the many astable circuits which can be built using logic gates. Most astables use RC networks to control the frequency of pulses. However, if an exact frequency is needed, crystal-controlled astables are used.

 
 


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3.1 RC networks

Most astables use resistor/capacitor, or RC, networks to control the frequency of the pulses produced. To understand how astables work, you need to know something about the properties of RC networks. This Section outlines the essential theory.

3.1.1 Charging

The diagram below shows a test circuit in which the capacitor, C, can be charged and discharged through the resistor, R:

Charging and discharging a capacitor

Changes in voltage depend on the size of the capacitor and are also controlled by resistor R. If the switch S1 has been in the discharge position for some time, as illustrated, all the charge stored on the capacitor will have drained away. The capacitor is empty and VC=0.

What happens when S1 is switched to charge? At the instant of switch over, the full 9 V appears across R. The initial charging current is given by:

initial charging current

As charge starts to accumulate, VC increases. When VC=3 V, the voltage across R is 9-3=6 V and the charging current becomes:

When VC=6 V, the voltage across R is 9-6=3 V and the charging current is smaller again.

In other words, charging is rapid at first, but decreases progressively as charging continues. This gives the charging curve a characteristic shape, as follows:

Charging graph

Click the button to draw the graph. The moment the switch closes is referred to as t0.

This is one of a family of exponential curves, all of which involve the number e, the base number for natural logarithms. The mathematical formula for the charging graph is:

capacitor charging

where t is the time elapsed since the application of voltage V. R is the value of the resistor and C is the value of the capacitor in the RC network. The quantity RC, resistance multiplied by capacitance, is called the time constant, , of the network. That is:

time constant

These equations work with fundamental units, time in seconds, voltage in volts, resistance in ohms, and capacitance in farads. To calculate the time constant, it is often useful to work with alternative units, as follows:

R units C units
Ω F s
μF s
μF ms
nF μs

As you can see, with R in MΩ and C in μF, the time constant works out in seconds, while with R in kΩ and C in μF, the time constant will be in milliseconds, ms.

What will be the time constant for these pairs of values? R=1 MΩ, C=10 μF: R=1 MΩ, C=4.7 μF: R=10 kΩ, C=2.2 μF: R=100 kΩ, C=10 nF.

The time constant isn't the time taken to charge or discharge the capacitor completely. If t, the time elapsed, is equal to the time constant value, the voltage reached during charging is given by:

In other words, during the first time constant, the capacitor charges by 0.63, or 63% towards its target voltage. During the second time constant, the capacitor charges again by 63% towards its target voltage, and so on:

Charging graph showing time constant intervals

Overall, charging is 98% complete after 4 time constants, 4, and more than 99% complete after 5 time constants, 5.

A useful formula derived from the charging equation allows you to calculate the time taken for the voltage to change from one value, V1, to a second value, V2:

time taken to charge between two values

where V is the target voltage, 9 V in this case, and is the natural logarithm, logarithm to the base e, of the voltage ratio.

Suppose you want to find the time taken for the voltage across the capacitor to change from 0 V to 4.5 V:

0.69RC is the half-charge time of the RC network. The threshold of a 4000 series logic gate is usually around half the power supply voltage. For this reason, half-charge times and half-discharge times feature in the design equations for some types of astable built with these devices.

Calculate the time taken for the voltage to change between 2 V and 7 V when 9 V is suddenly applied to an RC network with R=1 MΩ and C=1 μF.

3.1.2 Discharging

Suppose S1 in the test circuit is returned to the discharge position:

Charging and discharging a capacitor

The capacitor which was charged fully to 9 V will now start to discharge through the resistor R. At the instant of switch over, 9 V appears across R and the discharge current will be maximum. However, as the capacitor starts to empty, the voltage across it decreases. The discharge current decreases and the voltage changes more and more slowly.

The discharge graph for the circuit looks like this:

Discharging graph showing time constant intervals

The mathematical formula for the discharge graph is:

capacitor discharging

To calculate the time taken to discharge from one voltage V1 to a second voltage V2, use the formula:

time taken to discharge between two values

This assumes that the capacitor is discharging towards 0 V. is the natural logarithm, logarithm to the base e, of the voltage ratio, as before.

The half-discharge time will be 0.69RC. Confirm this by working through the formula for V1=9 V, V2=4.5 V. Your calculator should have useful buttons for and .

 
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3.2 Pulse response of RC networks


 

Often, you will be interested in what happens when pulses meet an RC network. In the circuit below, a pulse input is connected to Vin and Vout is the voltage across the capacitor:

Resistor-input RC Network

This is a type of voltage divider, with C in the Rbottom position.

The essentials of voltage dividers are explained in Chapter 3 of Design Electronics. When the capacitor is empty, it behaves as a low resistance in the circuit. When the capacitor is charged, it behaves like a high resistance.

The response of the RC circuit depends on how the time constant compares with the frequency of the input pulses. Before you click the play button to draw the graphs, think what sort of graphs you expect to see. 0 and 1 represent LOW and HIGH voltage levels:

Pulse response of resistor-input RC network

The capacitor charges during the HIGH time of each pulse and discharges when Vin is LOW.

If the time constant is short, charging is completed early in the pulse. If the time constant is intermediate, the exponential shapes of the charging and discharging phases are obvious. If the time constant is long, charging is incomplete before the end of the pulse, and the overall amplitude of the output signal is reduced.

What happens if the positions of R and C in the voltage divider are reversed?

Capacitor-input RC network

Again, think about what sort of graphs you expect before clicking the play button:

Pulse response of capacitor-input RC network

Rapid changes in voltage are transferred cross the capacitor. If the capacitor has discharged so that the voltage on the Vout side of the capacitor is 0 V, the falling edge of the Vin pulse generates a negative spike. This spike can be suppressed by placing a diode in parallel with resistor R:

Spike suppression

With a silicon diode, the negative spike is clipped to -0.7 V, corresponding to the forward voltage of the diode:

Spike suppression pulse response

The inputs of 4000 series logic gates include an inverse parallel diode to protect them from negative voltage spikes and suppress, or 'clip', spikes in exactly this way.

Sometimes, the voltage divider is tied to the positive end of the power supply, instead of to 0 V:

Capacitor-input RC network tied to +9 V

As a result, Vout is centred around +9 V:

Pulse response of capacitor-input RC network tied to +9 V

If the power supply is +9 V, the positive spike on the rising edge of the pulse will reach +18 V.

Once again, the spikes can be limited by adding a diode in parallel with the resistor R:

Spike suppression
 
Spike suppression pulse response

If the capacitor is tied to +9 V, the input pulses are rounded off, as the capacitor charges and discharges:

Resistor-input RC network tied to +9 V
 
Pulse response of resistor-input RC network tied to +9 V

Knowing how RC networks behave makes it much easier to understand the operation of astable circuits, as described in the rest of this Chapter.

 
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3.3 NOT gate astables

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3.3.1 Simple NOT gate astable

One of the simplest astables is built using two NOT gates, or inverters, from a 4069 hex inverter IC:

NOT gate astable

You can build this circuit on prototype board, as follows:

down open in a new window 4069 available from Rapid Online 4069 pins NOT gate astable

Monitor the output of the astable at A using an oscilloscope. Set VOLT/DIV to 2 V/DIV and TIME/DIV to 2 ms/DIV. Use the DC setting of the oscilloscope. If you don't know about oscilloscopes you can find out from Using an oscilloscope.

With the component values shown, you should find that the period of the astable pulse is around 10 ms, with roughly equal HIGH and LOW times. if t=10 ms=0.01 s, the frequency of the pulses is f=1/t=1/0.01=100 Hz.

The value of R2 should be large compared with R1. The circuit works well if R2 is ten times the value of R1.

Move the oscilloscope probe to point B in the circuit, as indicated in the circuit diagram and in the prototype board layout. You can find out where 0 V is on the graph by switching the oscilloscope input to earth, , or GND.

The diagram shows how the waveforms at these two points are related:

Waveforms of NOT gate astable

VDD is the power supply voltage for the circuit.

The two NOT gates are wired in series so that if the output of the first gate goes LOW, the output of the second goes HIGH, VA, point A in the circuit.

This happens when the voltage at the junction of R1 and C, VB, point B in the circuit, reaches the threshold of the first gate.

The threshold of the NOT gate is close to 0.5 VDD. When VA goes HIGH, VB jumps to 1.5 VDD. The output of the first NOT gate goes LOW at this moment. C starts to discharge towards 0 V through R1. When it reaches 0.5 VDD the output of the first NOT gate snaps HIGH and the output of the second NOT gate snaps LOW. VB jumps to - 0.5 VDD. Now, C starts to charge towards VDD. When it reaches 0.5 VDD the output of the first NOT gate goes LOW and the cycle begins again.

The HIGH time of the output pulse can be calculated using the formula:

time taken to discharge between two values

Here V1=1.5 VDD. and V2=0.5 VDD:

Similarly, the LOW time of the output pulse can be calculated from:

time taken to charge between two values

Here V=VDD:

In other words, if the threshold of the NOT gate=0.5 VDD, the HIGH and LOW times of the output pulses are equal and the period of the pulses is 2x1.1R1C=2.2R1C.

The astable frequency is:

NOT gate astable

The frequency stablility of this astable is good. In other words, the frequency is not affected significantly by variations in the power supply voltage, VDD.

3.3.2 Changing the mark space ratio

The mark space ratio of a pulse waveform is given by:

mark space ratio

The shape of the waveform can also be described by the duty cycle:

duty cycle

The NOT gate astable described above gives approximately equal HIGH and LOW times, so the mark space ratio is 1.0.

The circuit can be modified to give HIGH and LOW times which can be varied independently:

Modifying mark space ratio

The diodes are connected so that R1 controls the HIGH time of the pulse, and R2 controls the LOW time:

HIGH time

LOW time

Modify your circuit, adding components and rearranging links as follows. The new links are shown in grey:

down up open in a new window 4069 pins Modifying mark space ratio

Monitor the output of the astable at A using an oscilloscope. Set VOLT/DIV to 2 V/DIV and TIME/DIV to 2 ms/DIV. Use the DC setting of the oscilloscope.

The pulse waveform has changed. The HIGH time is short, around 1 ms, compared with the LOW time, around 5 ms. Use the equations for tHIGH and tLOW to work out what the exact values should be.

Disconnect the power supply and reverse the directions of both diodes. Reconnect the power supply. What does the waveform look like now?

 
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3.4 Gated astables

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3.4.1 Gated astable: NAND gate version

A gated astable can be turned on and off using a control signal. Using NAND gates in place of NOT gates gives one version of gated astable:

Gated astable using NAND gates

Build this circuit on prototype board as follows:

down up open in a new window 4011 available from Rapid Online 4011 pins Gated astable using NAND gates

Monitor the output of the astable at A using an oscilloscope. Set VOLT/DIV to 2 V/DIV and TIME/DIV to 2 ms/DIV. Use the DC setting of the oscilloscope.

Before you operate the push switch, the 100 kΩ pull down resistor holds one of the inputs of the first NAND gate at logic 0, with the result that the output of the first NAND gate remains at logic 1 regardless of the logic state of the second input:

input B input A output
0 0 1
0 1 1
1 0 1
1 1 0
NAND gate truth table

The second NAND gate is connected as a NOT gate so that the output of the astable, point A in the circuit, is LOW.

Pressing the switch connects the NAND gate input to logic 1 and enables the astable. Now, changes in the logic state of the second input do affect the logic state of the NAND gate output.

The frequency of the astable is calculated in the same way as for the NOT gate astable:

astable frequency

Remember about compatible units:

R units C units f
Ω F s Hz
μF s Hz
μF ms kHz
nF μs MHz

With R1=47 kΩ and C=100 nF=0.1 μF:

With the component values shown, you should find that the period of the astable pulse is around 10 ms, with roughly equal HIGH and LOW times.

The value of R2 should be large compared with R1. The circuit works well if R2 is ten times the value of R1.

3.4.2. Pulse completion: NAND gate version

With the circuit described above, pulses stop immediately when you release the button. Any noise at the input will give spurious signals at the astable output. This can be avoided by adding diodes to the circuit as follows:

Gated astable with pulse completion using NAND gates

The diodes and the 100 kΩ resistor form an OR gate. Pin 1 of the 4011 is HIGH if S1 is pressed, OR if the output of the astable, pin 4, point A, is HIGH. The astable remains enabled when S1 is released until the final astable pulse is complete.

It is easy to modify your prototype board layout:

down up open in a new window 4011 pins Gated astable with pulse completion using NAND gates

Monitor the astable output using an oscilloscope. Press and release the switch. If you can't see pulse completion in action, try replacing C with a larger value, 220 nF, or 470 nF.

Check on what is happening at point B in the circuit, between C and R1.

 

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3.4.3. Gated astable: NOR gate version

The circuit for a NOR gate gated astable is almost identical to the circuit using NAND gates:

Gated astable using NOR gates

The voltage divider at the input is the other way up. The 100 kΩ acts as a pull up resistor so that the input is held HIGH unless S1 is operated. From the truth table for NOR, you can see that this means the output of the first gate will be at logic 0 regardless of the logic state of the other input.

input B input A output
0 0 1
0 1 0
1 0 0
1 1 0
NOR gate truth table

The second NAND gate is connected as a NOT gate so that the output of the astable, point A in the circuit, is HIGH. Pressing S1 enables the astable and pulses start. When S1 is released, the output of the astable returns to HIGH.

 

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You can convert the prototype board from the NAND gate version to the NOR gate version by inserting a 4001 quad NOR gate IC in place of the 4011, and by rearranging the switch connections:

down up open in a new window 4001 available from Rapid Online 4001 pins Gated astable using NOR gates

3.4.4. Pulse completion: NOR gate version

The pulse completion circuit uses diodes and an additional 100 kΩ pull up resistor, as follows:

Gated astable with pulse completion using NOR gates

The diodes point in the opposite direction compared with the NAND gate version. Together with the pull up resistor, this arrangement has the properties of an AND gate. When S1 is released, the input becomes HIGH, logic 1. However, if the output of the astable is LOW, pin 1 of the 4001 remains LOW. If a pulse is in progress, this is completed before the astable is shut off.

It is easy to convert your existing prototype board for gated astable operation:

down up open in a new window 4001 pins Gated astable with pulse completion using NOR gates

Once again, monitor the output of the astable using an oscilloscope and find out what happens when you press and release S1.

All of these gated astable circuits can be controlled by a gating signal from some other electronic circuit. Remove S1 from the circuit amd connect your gating signal in its place.

 
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3.5 Ring-of-three astables

Two stage astables are suitable for many applications but can cause problems with fast-acting counting and dividing circuits. Two stage astables can pick up supply line noise as the gates change state, sometimes producing square waves with distorted leading and trailing edges. Three stage, or ring-of-three astables eliminate this type of distortion and are much better as clock generators for counting and didiving circuits.

3.5.1 Ring-of-three astable using NOT gates

The diagram shows the circuit of a ring-of-three astable using NOT gates:

Ring-of-three astable using NOT gates

R1 and C are the timing components. These still form a voltage divider with the centre point connected to the input of the astable, via R2. However, the positions of R1 and C are reversed compared with the two stage NOT gate astable.

Together, the first two NOT gates form a very high gain non-inverting amplifier stage which helps to switch the astable cleanly from one logic state to the other.

The formula for calculating the frequency of a ring-of-three astable is the same as for two stage astables:

astable frequency

The value of R2 should be much larger than R1. 10 times larger is a good general rule.

You can build the ring-of-three astable on prototype board, as follows:

down up open in a new window 4069 available from Rapid Online 4069 pins Ring-of-three astable using NOT gates

Ring-of-three astables can be built with NAND and NOR gates and can be modified in just the same ways as two stage astables. For example, you can modiy the mark space ratio, and make gated astables, or astables with pulse completion.

3.5.2 Ring-of-three gated astable using NAND gates

The NAND gate version of the ring-of-three astable is gated ON by a HIGH voltage, logic 1:

Ring-of-three gated astable using NAND gates

The gating signal is usually applied to the second NAND gate. With this pattern of connection, the output of the astable is LOW unless S1 is operated.

Build the circuit on prototype board as follows:

down up open in a new window 4011 pins Ring-of-three gated astable using NAND gates

Check the astable output by connecting an oscilloscope as indicated and investigate the effect of pressing and releasing S1.

Modify your circuit so that the gating signal is applied to the first NAND gate instead of the second. You should find that the output of the astable is HIGH unless S1 is operated.

3.5.3 Ring-of-three gated astable using NOR gates

The gating input is held HIGH and becomes LOW when S1 is pressed:

Ring-of-three gated astable using NOR gates

The prototype board layout needs little alteration, Replace the 4011 NAND gate IC with a 4001 NOR gate IC and rearrange the voltage divider at the input:

down up open in a new window 4001 pins Ring-of-three gated astable using NOR gates

Connect an oscilloscope and find the effect of pressing S1. With gating applied to the second NOR gate, the output of the astable is HIGH unless the astable is enabled by pressing S1.

What happens if you rearrange the circuit so that gating is applied to the first NOR gate?

3.5.4 Pulse completion

Either circuit can be modified for pulse completion:

Ring-of-three gated astable with pulse completion using NAND gates
 
Ring-of-three gated astable with pulse completion using NOR gates

The diagram shows the NAND gate version of the pulse completion circuit:

down up open in a new window 4011 pins Ring-of-three NAND gate astable with pulse completion

Your prototype board is easily modified to give this result. Investigate the behaviour of the circuit using an oscilloscope. Contemplate building a ring-of-three NOR gate astable with pulse completion.

 
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3.6 Astables with two RC networks

3.6.1 NOT gate astable

Quite often astables are made using two logic gates interlinked by capacitor-input RC networks. This NOT gate astable is the simplest example:

NOT gate astable

The resistors at the bottom of both RC networks are tied to 0 V. This changes the behaviour of the circuit compared with those described above. The HIGH and LOW times of the output pulse, pin 4 of the 4069 in the diagram, are given by:

These are the half charge/discharge times of the RC networks. The astable frequency is given by:

To understand better how the circuit works, build it on prototype board:

down up open in a new window 4069 pins NOT gate astable

Use the oscilloscope to investigate the waveforms at pins 1, 2, 3 and 4 of the 4069. Pin 4 is the final output of the astable. How does the signal here compare with the signal at pin 2, the output of the first NOT gate?

What should be the HIGH and LOW times of the output pulses for the component values shown? What should be the frequency of the astable? Use your calculator to find out.

The diagram below shows how the waveforms at different points in the circuit are related:

Waveforms of NOT gate astable

The negative going parts of the signals at the inputs to the two gates are clipped by protection diodes which form part of the internal circuit. Voltages at the two inputs change slowly, making this astable vulnerable to supply line noise.

The circuit will also work with the resistors tied to the positive power supply rail:

NOT gate astable with RC networks tied to +9 V

3.6.2 Gated astable using NAND gates

To create a gated astable on this model using NAND gates, the resistors must be tied to the positive power supply rail:

Gated astable using NAND gates

To build this on prototype board, it makes sense to use the gates on the right hand side of the 4011, closer to the positive power supply rail:

down up open in a new window 4001 pins Gated astable using NAND gates

Operate the switch and probe the inputs and outputs of the gates with the oscilloscope to find out how the circuit works.

3.6.3 Gated astable using NOR gates

For the NOR gate version of the circuit, the resistors must be tied to 0 V and the gating input is held HIGH unless S1 is pressed:

Gated astable using NOR gates

This time, it is more convenient to use the gates on the left hand side of the integrated circuit:

down up open in a new window 4001 pins Gated astable using NOR gates
 
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3.7 Schmitt trigger astables

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The properties of Schmitt trigger logic gates are outlined in Chapter 2 of Discovering Digital Electronics, where the NOT gate version of the Schmitt trigger astable is described in detail.

You can make a gated astable using just one Schmitt trigger NAND gate:

Gated astable using Schmitt trigger NAND gate

The 4093 4093 available from Rapid Online Schmitt trigger quad 2-input NAND gate is useful integrated circuit. The layout of the gates inside is the same as with the 4011, and other quad 2-input devices. The two thresholds are typically at 1/3 and 2/3 of the power supply voltage.

Build the prototype board version of the circuit as follows:

down up open in a new window 4093 available from Rapid Online 4093 pins Gated astable using Schmitt trigger NAND gate

The transistor/LED indicator allows you to see the pulses.

As explained in Chapter 2, assuming the Schmitt trigger thresholds are located at 1/3 and 2/3 of the power supply voltage, the HIGH and LOW times of the astable pulse output each correspond to a half charge time, 0.69RC. The period of the pulse waveform is 0.69RC + 0.69RC and the frequency of the pulses is given by:

Schmitt astable

In practice, the Schmitt trigger thresholds are not fixed exactly and it is better to approximate the frequency as:

Schmitt astable

With the component values shown, the LED should flash at about 10 Hz. Use the oscilloscope to investigate the waveforms at pin 3 of the 4093, the output of the astable, and at pin 2, where you can see the capacitor charging and discharging.

You might just be able to tell that the LED is illuminated for longer when S1 is first pressed. To understand why click to draw the graph:

Graph showing Schmitt trigger astable input and output voltages

Initially, the capacitor is empty and must charge from 0 to 6 V to reach the first Schmitt trigger threshold. When this is reached, the output of the NAND gate snaps LOW and the capacitor starts to discharge. When the second threshold is reached, close to 3 V with a 9 V power supply, the output of the NAND gate snaps HIGH once more. This time, the capacitor is already partly charged and the duration of the second pulse corresponds with the time take to charge from 3 V to 6 V.

Since an astable needs just one of the four NAND gates in the 4093, the remaining gates can be used for other things. Simple DOCTRONICS projects based on the 4093 include the Biscuit Tin Alarm and chuckles Chuckles, a circuit which makes a silly noise.

 
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3.8 Crystal-controlled astables


If you want an accurate astable, for example, as part of a digital clock circuit, you are going to need a crystal-controlled astable.

Crystals are available in a wide range of frequencies. Most have high resonant frequencies, 1 MHz or more, although special purpose watch crystals are available with a resonant frequency of 32,768 Hz, 215 Hz.

Typically, frequencies are accurate to 30 ppm, parts per million. Astables which use RC networks will be accurate to 5% at best, equivalent to 50,000 parts per million!

The diagram shows a crystal-controlled astable using NOT gates:

Crystal-controlled astable using NOT gates

Build this on prototype board as follows:

down up open in a new window 4069 pins Crystal-controlled astable using NOT gates
 

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You will need an oscilloscope to find out whether your circuit works. With a 2 MHz crystal, the period of the waveform is just 0.5 μs. The output signal from pin 4 of the 4069 won't look much like a square wave. However, after a few stages of binary division, clean accurate square wave signals will be generated.

Because crystal-controlled circuits use small value capacitors, testing on prototype board is not ideal. A capacitor consists of two bits of metal, conductor, separated by a space filled with an insulator. The metal channels of the prototype board introduce stray capacitance which can affect circuit performance.

The photograph shows the bits and pieces you can find inside a digital watch:

watch components
Inside a digital watch

Can you see the crystal at the bottom of the watch PCB? The black blobs on the PCB cover the integrated circuits which control the operation of the watch. Digital watches are made in such enormous numbers that they have become cheap to buy. Nevertheless, they are sophisticated and complex devices.

If you have an old digital watch you can take to pieces, try to work out how the external switches connect with the PCB and how the PCB is in turn connected to the display.

The 4060 4060 available from Rapid Online is a useful device with an astable which can be controlled by an external crystal:

4060 Internal arrangement

The 4060 can be used with an RC network, as explained in the 4060 Beastie Zone, however, you can add external components to make a crystal-controlled astable:

4060 Crystal-controlled astable
 

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To build the prototype board version of this circuit, you can substitute a 15 pF capacitor for the trimmer:

up open in a new window 4060 available from Rapid Online 4060 pins Crystal-controlled 4060 astable

You can see that +9 V and 0 V are both connected on the right hand side of the prototype board. This is useful if you need to make connections to 0 V from the right hand side of the integrated circuit.

the circuit uses a watch crystal which resonates at 32,768 Hz=215 Hz. At the first available output, pin 7, the crystal frequency has already been divided by 24=16. That is, the frequency is 2048 Hz. Monitor this output with the oscilloscope and confirm that the period of the waveform is around 0.5 ms=500 μs. If you have access to a frequency meter, you should be able to confirm that the frequency is exactly 2048 Hz.

It is interesting to move the oscilloscope probe along from one counter output to the next. Each time, the frequency is halved and the period of the waveform is doubled. Note that output 10, corresponding to division by 211, is not avialable externally and is therefore missing from the sequence.

Overall, the 4060 divides its input frequency by 214. With a watch crystal oscillator, the final output, pin 3, is at 2 Hz.

You will meet this IC again when you build the DOCTRONICS digital clock.

This Chapter has become a bit of an epic. Pretty much everything you need to know about building astables using 4000 series devices is here for you to refer to. Of course, you can make astables using the 555 timer. Transistor astables are also possible..

 
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3.9 What have you learned?


DOCTRONICS recommends:

  • The theory of charging and discharging capacitors is outlined. You should be able to explain how the time constant affects charging and discharging graphs.
  • The pulse response of RC networks depends on the time constant. You should be able to distinguish between resistor-input and capacitor-input networks.
  • Diodes can be used to limit voltage spikes above or below the power supply limits.
  • Simple astables using one RC network can be built with two NOT gates. The astable frequency is given by:
    NOT gate astable
  • The circuit of a simple astable can be modified to change the mark space ratio.
  • It is easy to make gated astables using NAND gate, or NOR gate, versions of the simple astable.
  • Pulse completion versions of these astables can be made by adding diodes to the circuit.
  • Ring-of-three astables give improved performance by speeding up the rising and falling edges of the astable pulses. The design formula for the astable frequency is the same as for the simple astable:
    NOT gate astable
  • Gated and pulse completion versions of ring-of-three astables can be built.
  • Astables with two RC networks have no performance advantages, but are easy to understand and give independent control of HIGH and LOW times. The astable frequency is given by:

  • A Schmitt trigger NOT gate can be used to build a very simple astable circuit. The frequency of the pulses is approximated by 1/RC.
  • A gated astable can be built with just one Schmitt trigger NAND gate.
  • Crystal-controlled astables are extremely accurate.
  • the 4093 quad 2-input Schmitt NAND and the 4060 oscillator counter/divider are useful devices worth remembering.
  • Astables can be made with other devices, including the 555 timer.
 
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