Doctronics

 5 : BISTABLES

A bistable circuit, also called a latch, or 'flip-flop', has two stable states. The output of a bistable can be either logic 1 or logic 0 according to signals received at its inputs.

Bistables of various types are the fundamental building blocks of memory and of electronic counting circuits, and of much else in the world of digital electronics, as you will discover.

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One of the simplest bistable circuits consists of two NAND gates:

As you can see, there are two inputs, the SET, S and RESET, R. The 'bars' over these symbols indicate that these inputs are active-LOW. In other words, each input must be held HIGH and pulsed LOW when you want something to happen.

Q and Q, or NOT-Q, are the outputs of the circuit and normally have opposite logic states.

The bistable is SET when Q=1 and Q=0, and RESET when Q=0 and Q=1.

This kind of bistable is called a set-reset bistable, S R bistable, or sometimes R S bistable, latch or flip-flop and is often represented by a simplified symbol, as follows:

A practical circuit for a NAND gate bistable needs switches to provide logic signals. Since the SET and RESET inputs are to be held HIGH and pulsed LOW, you need switches with pull up resistors as indicated in the circuit diagram which follows:

It would be useful to monitor the Q and Q outputs with LEDs which illuminate when each output is HIGH:

Remember that the outputs of the NAND gates driving the LEDs do not produce valid logic signals.

As you can see, the whole circuit requires four NAND gates and can therefore be assembled using a single 4011 CMOS integrated circuit. The prototype board layout for this is shown below. Go ahead and build the circuit, following the layout carefully:

NAND gate bistable with LED indicators

Look at the way in which the push button switches are connected on the prototype board. The placement of link wires to the inputs of the 4011 NAND gates exploits the way in which the contacts are arrranged inside the switch. As you can see in the diagram below, the top two pins of the switch are internally connected by a metal strip:

The bottom two pins are connected in the same way. As a result, either pin from each pair can be used to make connections to other parts of the circuit. This is a common arrangement for push button switches intended for use on printed circuit boards, PCBs, and helps to simplify the design of PCB layouts for keyboard circuits.

Test your set-reset bistable:

• What happens when you operate the SET push button?
• What happens when you operate the RESET push button?
• What happens when you operate both buttons at once?

In this last condition, both Q and Q LEDs should illuminate. This is often described as a 'disallowed state'. The bistable isn't damaged, but it is impossible to predict which ouptut will remain HIGH when the buttons are released.

A set-reset bistable is often used as a 'memory' device, for example in a burglar alarm, which remains ON once it has been triggered.

A set-reset bistable can be made using NOR gates, as explained later in this Chapter and also in the 4001 page of the Beastie Zone.

A different application for a set-reset bistable is in 'debouncing' a switch. The metal contacts inside a switch are springy and often bounce when the switch state is altered. Contacts may close not once, but several times. The diagram below shows what you might see at the inputs and outputs of the bistable using an oscilloscope to monitor voltage/time changes. Click 'play' to start the animation:

Although the signals at the SET and RESET inputs change several times, the Q output changes just once from LOW to HIGH, and once from HIGH to LOW. In this way, you can produce 'debounced' output pulse. Pressing the SET switch gives a rising edge, pressing the RESET switch gives a falling edge.

An alternative debouncing circuit using Schmitt trigger NOT gates is described in Chapter 4.

Don't dismantle your prototype board layout, you are going to add to it in the next section.

For electronic counting, a more sophisticated type of bistable is needed. The diagram below shows the connections for a D-type bistable:

As you can see, there are four different inputs:

• The DATA input is held at logic 1 or logic 0 and can be changed from one logic state to another at any time.
• The small triangle inside the symbol indicates that the CLOCK input is edge-triggered. This is an important property. The CLOCK input of a D-type bistable responds only to rising edges, that is, a rapid change from LOW to HIGH. Slow changes and sustained HIGH or LOW signals have no effect.
• The S and R inputs are the SET and RESET. The absence of 'bars' above these inputs indicates that they are 'active HIGH'. In other words, S and R should be held LOW and pulsed HIGH to SET and RESET the bistable.
• Q and Q are the outputs as before

To describe the action of a D-type bistable, you can say that the logic state at the DATA, or D, input is transferred to the Q output on the rising edge of the CLOCK signal.

This statement is easier to understand once you have built and tested a prototype circuit. Add a new prototype board to your existing arrangement:

Testing a D-type bistable

The new part of the circuit uses a 4013B CMOS integrated circuit. The 4013 contains two separate D-type bistables with pin connections as follows:

For the present, you are going to use the D-type bistable connected to pins 1-6, leaving the other bistable unconnected. In any final circuit, all unused CMOS inputs must be connected either to +9 V or 0 V, but you can usually work on prototype board without worrying about the unused parts of the integrated circuit.

Build the D-type circuit, following the layout carefully. Click to open a PDF version of the drawing which can be printed out, if this helps.

Connect the power supply and the CLOCK input from the first prototype board as shown, then investigate the action of the D-type:

• Verify the action of the D-type SET and RESET switches

Whenever these switches are pressed, the output of the D-type will change accordingly. The SET and RESET inputs are 'level sensitive', rather than edge triggered.

• What happens if SET and RESET are pressed simultaneously?

This is a disallowed state, as with the NAND gate bistable. When the switches are released, you can't predict which states the outputs of the bistable will adopt,
Q=1:Q=0 or Q=0:Q=1.

• Press the RESET switch to force Q=0, then connect the DATA input to+9 V, using a 'flying lead' from the prototype board.
• Press the RESET switch on the NAND gate bistable (first prototype board) and then press the SET switch on the NAND gate circuit. This produces a rising edge at the CLOCK input of the D-type bistable, provided you have connected the two prototype boards together.
  

At the exact moment that the rising edge occurs, the Q output of the D-type bistable will go HIGH.

• Disconnect the flying lead from +9 V. Because of the pull down resistor, the DATA input immediately returns to LOW. Does this have any effect on the ouputs of the D-type?
• Repeat the RESET/SET sequence with the NAND gate circuit.

Again the output of D-type changes at the exact moment that the rising edge arrives. This is what is meant by edge triggered behaviour.

Continue to investigate the D-type until you are confident that you understand what each of the inputs and outputs will do.

Don't take your carefully assembled prototype board circuits to bits. You will need them both for the practical work described in this section.

Electronic counting depends on toggle bistables. This isn't an entirely new variety of bistable you need to learn about, but is easily made by connecting the Q output of a D-type bistable to its DATA input, as follows:

The special property of a toggle bistable is that its output changes state every time an input pulse arrives.

You can convert your D-type bistable circuit to a toggle bistable by removing one link and inserting another. Do this now:

Testing a toggle bistable

There is a new link from NOT-Q, Q, to the DATA input and the connection to the second LED has been removed. Keep the connections with the NAND gate bistable circuit.

• RESET the NAND gate bistable and then press SET and RESET in sequence repeatedly in order to deliver a series of input pulses to the CLOCK input of the toggle bistable.

The output of the toggle bistable changes state for each input pulse received, Strictly, for each rising edge received. With an oscilloscope, the changes observed are like this:

Click play to start the animation. As you can see, the Q output changes state at the beginning of each input pulse. You should be able to see this happen when you press the NAND gate bistable SET button.

• Count the input pulses in the diagram above.

Answer: 4

• Count the output pulses in the diagram above.

Answer: 2

The toggle bistable divides the number of input pulses by two. This is really the same as counting the input pulses. To make this clear, you can now add a second toggle bistable to the first:

Connecting toggle bistables to make a counter

Add the links following the layout carefully. Your circuit is now:

The output of the first D-type is a pulse waveform with rising edges and these trigger the second bistable as follows:

You have added a second divide-by-two circuit, with one Q2 output pulse for every four input pulses.

It is helpful to convert these waveforms into truth table format, with each line in the truth table corresponding to one of the numbered arrows at the bottom of the diagram:

In the truth table, the Q1 output is shown in the right hand column because it is the least significant bit, or LSB, of a binary number. The repeated counting sequence, indicated by shading, is 11 10 01 00, in descending binary order.

You have built a 2-bit binary down counter. There are 2 D-types and 2²=4 different output states.

How could you make a 3-bit binary down counter? Easy! Add another toggle bistable:

How many output states would this have? The calculation is 2³=8 output states. For a 4-bit counter (2⁴=16 ouptut states) you would add a fourth bistable and so on.

This is all very well, but how can you make an up counter, which is likely to be more useful for counting in general and for electronic clock circuits in particular? This is easier than it sounds. All you need to do is to rearrange the connections between the toggle bistables. Instead of connecting the Q output to the CLOCK input of the next stage, the Q output is connected to the CLOCK input of the next stage. The circuit becomes:

The down counter prototype board layout is easily modified to make an up counter:

2-bit binary up counter, Q to CLOCK

Remove the Q1 to CLOCK link and replace it with a NOT-Q1, Q1, to CLOCK link, indicated here in blue.

The waveforms at the counter outputs are changed to:

The truth table for the counter outputs is changed as well and the outputs now follow the sequence 00 01 10 11, that is, binary numbers in ascending order:

The shaded part of the table show the repeated sequence. Notice again that the Q1 output appears at the right hand side because it is the LSB of the binary number.

Confirm the behaviour of your up counter by sending pulses from the NAND gate bistable, as before.

Here is the circuit for a 3-bit binary up counter:

To make a 4-bit binary up counter, you add a fourth toggle bistable connected in the same way, and so on.

To summarise:

• DOWN counter: Q to CLOCK input of next stage
• UP counter: Q to CLOCK input of next stage

You will find out more about counters in due course. The counters described in this Chapter count only in powers of two, 2²=4, 2³=8, 2⁴=16, and so on. How can you make a decimal counter which counts in 10's? How could you link counters together to count up to 100, or to 60, to count seconds or minutes, or to 12 or 24 for hours? Similarly, how can you process the outputs of counters to give a user-friendly display?

All these questions have answers and, as you work through the next few Chapters of Discovering Digital Electronics, you will find out what they are.

A set-reset bistable can be implemented using NOR gates instead of NAND gates. A practical circuit, including LED indicators, looks like this:

The SET and RESET inputs are active-HIGH, that is, the inputs are held LOW and pulsed HIGH to SET or RESET the bistable. Q and Q, or NOT-Q, are the outputs of the circuit and normally have opposite logic states.

Build the circuit on prototype board as follows:

NOR gate bistable with LED indicators

The circuit uses four NOR gates and can be built using a 4001 quad NOR gate integrated circuit.

You can build a monostable using NAND gates following this circuit:

The trigger input is held HIGH and pulsed LOW by pressing the trigger switch. The period of the monostable pulse is determined by R and C and, assuming the switching threshold of the 4011 gates is half the power supply voltage, the period of the pulse will be:

The monostable output pulse is positive-going at and negative-going at .

To understand how the monostable works, think first about the truth table for a NAND gate:

When the circuit is in its resting state, capacitor C is discharged via resistor R so that the input to the second NAND gate, pins 5 and 6, is held LOW. The output of this gate, , is HIGH.

The 100 kΩ pull up resistor in the input voltage divider holds pin 2 of the 4011 HIGH unless the push switch is operated. In the resting state, both inputs of the first NAND gate are held HIGH and its output is LOW.

Operating the push switch briefly causes the output of the first NAND gate to snap HIGH while the output of the second NAND gate snaps LOW. The ouptut of the second NAND gate remains LOW until the capacitor discharges to the threshold voltage at the input of the gate.

Click 'play' in the animation to see the waveforms for this circuit:

The trigger pulse is usually shorter than the output pulse of the monostable. If it is longer the output of the monostable remains in its active state until the trigger pulse terminates.

Operate the push button to trigger the monostable. How could you double the period of the monostable pulse?

The circuit below shows how a RESET input can be added to the NAND gate monostable:

. The timing capacitor has been increased to 10 μF.

Operate the trigger switch as before and confirm that the monostable period has been increased to around 7 s. Operate the trigger switch again and then press the RESET switch. The monostable output pulse terminates immediately.

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With appropriate changes to the circuit, NOR gates can be used to make a monostable:

In the trigger input voltage divider, the 100 kΩ is a pull down resistor. R and C are the timing components and, as with the NAND gate monostable, the period of the output pulse is given by:

Before clicking 'play' in the animation, think about the waveforms you would expect in this circuit:

To understand how the monostable works, think about the truth table for a NOR gate:

When the circuit is in its resting state, both inputs to the first NOR gate are LOW and its output is HIGH. The trigger pulse is positive-going. What effect will this have on the output of the first gate?

Pins 5 and 6 are held HIGH by resistor R and drop LOW when the output of the first gate changes. Capacitor C starts to charge and when the gate threshold is reached, the output pulse is terminated.

Build the circuit on prototype board as follows:

NOR gate monostable

The prototype board layout is different from the NAND gate version. Note the polarity of the 4.7 μF capacitor. One end of the 1 MΩ resistor is tied to +9 V.

Operate the miniature tactile switch to see the monostable in action.

The circuit is easily modified to include a RESET input:

Modify the prototype board version of the circuit as follows:

NOR gate monstable with RESET input

It is instructive to build some of these circuits on prototype board. Remember that you can open any of these drawings in its own window. Right-clicking gives you the option to print out the layout so that you can follow a paper version if the electronics lab is a long way from the computer room.

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A retriggerable monostable circuit allows you to initiate a new monstable pulse before any ongoing pulse has been completed. One version uses a 555 timer . This is not a logic gate circuit but can help you to understand what is meant by retriggering:

As you can see, a PNP transistor, BC557B, has been included in the trigger circuit. To understand how the circuit works click 'play' in the animation:

The first trigger pulse results in a normal ouput pulse with a period determined by t=1.1RC. Note that the timing capacitor is fully discharged during the trigger pulse: the timing period starts when the trigger input goes HIGH.

The second trigger pulse is followed by a third and then a fourth before the normal output period has been completed. The additional trigger pulses discharge the timing capacitor, giving an extended output pulse.

To see the circuit in action, build it on prototype board, as follows:

Retriggerable monostable circuit

Operate the push switch. The normal output of the monostable should be around 5 s. When the LED switches OFF, press the push switch again and then press is once more after 2-3 s.

Provided you keep pressing the switch at intervals of less than 5 s, the output LED remains ON.

If the input voltage divider is replaced by a source of pulses, this circuit can be used as a 'missing pulse' or 'low rate' detector. Any decrease in the frequency of the input pulses below the design level, will allow the monostable to complete its cycle, driving the output LOW.

More information on the 555 timer is provided at: www.doctronics.co.uk/555.htm.

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The 4538B is a special purpose IC containing two monostables which can be used independently. The pin connections for the 4538B are as follows:

Pin connections for monostable A are on the left hand side of the IC, with pins for monostable B on the right. The next diagram shows these connections in more detail:

Each monostable has two trigger inputs. The monostable can be triggered/retriggered by a rising edge at provided is held HIGH. Alternatively, the monostable can be triggered/retriggered by a falling edge at provided is held LOW.

The two outputs have opposite logic states. In its resting or quiescent state, output is LOW: goes HIGH during the monostable pulse. Output is normally HIGH and goes LOW during the monostable pulse.

is an overriding active LOW direct reset input. In other words, the output of the monostable is reset, forcing output LOW, whenever is LOW, regardless of the logic states of the trigger inputs.

This behaviour can be summarised in truth table form:

inputs			outputs
	L	H
H		H
X	X	L	L	H

where:

H = HIGH state (the more positive voltage)
L = LOW state (the more negative voltage)
X = state is immaterial
= positive-going transition (rising edge)
= negative-going transition (falling edge)
= positive output pulse
= negative output pulse

The timing components are connected to and as follows:

The period of the output pulse is given by:

To test one of monostables inside the 4538B, you need to add suitable trigger and indicator circuits. With CMOS logic, power supply decoupling is essential:

Build the circuit on prototype board, as follows:

R4538B test circuit

Check the pin connections of the 4538 by clicking . From the function table, which mode of operation is selected?

Operate the push switch to trigger the monostable. Is the monostable retriggered if you press the button again before the timing period is complete? Experiment to see if you can change the mode of operation so that the monostable is triggered by a falling edge. You will need to rearrange the resistor/switch voltgae divider as well as the connections to the trigger inputs, pins 4 and 5.

The 4538 is a versatile device and is a good choice if you need short pulses linked to particular events in a complex logic circuit.

Other monostable circuits are described in the beastie zone pages for the 555 timer and the 4060 counter/divider.

DOCTRONICS recommends:

• A monostable produces a single pulse when triggered.
• Edge detectors, or half monostables, generate a pulse corresponding to the rising or falling edge of a longer period pulse waveform.
• Edge detectors are built using Schmitt trigger logic gates and can be designed to give positive-going or negative-going output pulses. The period of these pulses approximates to the two thirds charge/discharge time set by the timimg components:
  
• Monostables can be built with NAND gates and NOR gates. The monostable period is determined by:
  
• RESET inputs can be added to these circuits, allowing the monostable output pulse to be terminated early.
• A retriggerable monostable circuit allows you to initiate a new monostable pulse before any ongoing pulse has been completed. One easy to understand version uses a 555 timer.
• The 4538B dual precision monostable is a versatile device containing two retriggerable monostables which can be used independently. Trigger inputs can be programmed for rising edge or falling edge triggering.
• Monostables can be made with other devices, including the 555 timer and 4060 counter/divider.